標題: | Low-Complexity Digit-Serial Multiplier Over GF(2(m)) Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition |
作者: | Lee, Chiou-Yng Meher, Pramod Kumar Fan, Chia-Chen Yuan, Shyan-Ming 資訊工程學系 Department of Computer Science |
關鍵字: | Karatsuba algorithm;shifted polynomial basis (SPB);Toeplitz matrix-vector product (TMVP) |
公開日期: | 二月-2017 |
摘要: | In this paper, we have shown that a regular Toeplitz matrix-vector product (TMVP) can be transformed into a Toeplitz block TMVP (TBTMVP) using a suitable permutation matrix. Based on the TBTMVP representation, we have proposed a new (a, b)-way TBTMVP decomposition algorithm for implementing a digit-serial multiplication. Moreover, it is shown that, based on iterative block recombination, we can improve the space complexity of the proposed TBTMVP decomposition. From the synthesis results, we have shown that the proposed TBTMVP-based multiplier involves less area, less area-delay product, and higher throughput compared with the existing digitserial multipliers. |
URI: | http://dx.doi.org/10.1109/TVLSI.2016.2605183 http://hdl.handle.net/11536/133186 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2016.2605183 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 25 |
Issue: | 2 |
起始頁: | 735 |
結束頁: | 746 |
顯示於類別: | 期刊論文 |