完整後設資料紀錄
DC 欄位語言
dc.contributor.authorWang, I-Tingen_US
dc.contributor.authorChang, Chih-Chengen_US
dc.contributor.authorChiu, Li-Wenen_US
dc.contributor.authorChou, Teyuhen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.date.accessioned2017-04-21T06:55:21Z-
dc.date.available2017-04-21T06:55:21Z-
dc.date.issued2016-09-09en_US
dc.identifier.issn0957-4484en_US
dc.identifier.urihttp://dx.doi.org/10.1088/0957-4484/27/36/365204en_US
dc.identifier.urihttp://hdl.handle.net/11536/134237-
dc.description.abstractThe implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaOx/TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.en_US
dc.language.isoen_USen_US
dc.subjecthardware neural networken_US
dc.subjectelectronic synapseen_US
dc.subjectthree dimensionalen_US
dc.subjectRRAMen_US
dc.title3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applicationsen_US
dc.identifier.doi10.1088/0957-4484/27/36/365204en_US
dc.identifier.journalNANOTECHNOLOGYen_US
dc.citation.volume27en_US
dc.citation.issue36en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000384064400009en_US
顯示於類別:期刊論文