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dc.contributor.authorYou, Yi-Pingen_US
dc.contributor.authorChen, Szu-Chienen_US
dc.date.accessioned2017-04-21T06:55:23Z-
dc.date.available2017-04-21T06:55:23Z-
dc.date.issued2016-08en_US
dc.identifier.issn1539-9087en_US
dc.identifier.urihttp://dx.doi.org/10.1145/2961026en_US
dc.identifier.urihttp://hdl.handle.net/11536/134282-
dc.description.abstractGraphics processing units (GPUs) are now widely used in embedded systems for manipulating computer graphics and even for general-purpose computation. However, many embedded systems have to manage highly restricted hardware resources in order to achieve high performance or energy efficiency. The number of registers is one of the common limiting factors in an embedded GPU design. Programs that run with a low number of registers may suffer from high register pressure if register allocation is not properly designed, especially on a GPU in which a register is divided into four elements and each element can be accessed separately, because allocating a register for a vector-type variable that does not contain values in all elements wastes register spaces. In this article, we present a vector-aware register allocation framework to improve register utilization on shader architectures. The framework involves two major components: (1) element-based register allocation that allocates registers based on the element requirement of variables and (2) register packing that rearranges elements of registers in order to increase the number of contiguous free elements, thereby keeping more live variables in registers. Experimental results on a cycle-approximate simulator showed that the proposed framework decreased 92% of register spills in total and made 91.7% of 14 common shader programs spill free. These results indicate an opportunity for energy management of the space that is used for storing spilled variables, with the framework improving the performance by a geometric mean of 8.3%, 16.3%, and 29.2% for general shader processors in which variables are spilled to memory with 5-, 10-, and 20-cycle access latencies, respectively. Furthermore, the reduction in the register requirement of programs enabled another 11 programs with high register pressure to be runnable on a lightweight GPU.en_US
dc.language.isoen_USen_US
dc.subjectRegister allocationen_US
dc.subjectshader processorsen_US
dc.subjectregister packingen_US
dc.titleVecRA: A Vector-Aware Register Allocator for GPU Shader Processorsen_US
dc.identifier.doi10.1145/2961026en_US
dc.identifier.journalACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMSen_US
dc.citation.volume15en_US
dc.citation.issue3en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000384247100003en_US
Appears in Collections:Articles