Investigation of Hot Carrier Reliability of Ultrathin Poly-Si Nanobelt Junctionless (UTNB-JL) Transistors on Different Underlying Insulators

Abstract

In this work, we investigate the hot carrier stress (HCS) of ultrathin poly-Si nanobelt junctionless transistors on different insulator (TEOS and Si3N4). Time exponent n suggests the oxide trap charge is the dominant mechanism. The subthreshold slope (S.S.) is improved by acceptor-like interface states generated after HCS, and different S.S. improvement between JL_O and JL_N is caused by surface roughness of channel films resulting from nucleation during channel deposition in LPCVD step.