A Low Power 2.4/5.2GHz Concurrent Receiver Using Current-Reused Architecture

Abstract

This paper presents a low-power 2.4/5.2GHz concurrent receiver for emerging wireless sensing applications. The RF front-end design includes a concurrent dual-band low noise amplifier (LNA), a stacked mixer and VCO architecture, and variable-gain baseband amplifiers (VGA). Current-reused techniques, by sharing gain stages and stacked components, are explored in the receiver design for the further reduction of power consumption. The prototype chip, which was fabricated in a 0.18 mu m CMOS process, occupies a chip area of 3.67mm(2), including pads and impedance matching networks. At the 2.4GHz band, the proposed receiver achieves a maximum gain of 43dB, a noise figure of 8.9dB, and a 1-dB compression point (P1dB) larger than -34dBm. At the 5.2GHz band, the proposed receiver achieves a maximum gain of 31dB, a noise figure of 16.3dB, and a P1dB larger than -27dBm. The total power consumption is 7.3mW at a supply voltage of 1.2V.