標題: | A Low Power 2.4/5.2GHz Concurrent Receiver Using Current-Reused Architecture |
作者: | Hsu, Hung-Sheng Duan, Qiu-Yue Liao, Yu-Te 電機工程學系 Department of Electrical and Computer Engineering |
關鍵字: | CMOS;dual-band;low power;current-reused |
公開日期: | 2016 |
摘要: | This paper presents a low-power 2.4/5.2GHz concurrent receiver for emerging wireless sensing applications. The RF front-end design includes a concurrent dual-band low noise amplifier (LNA), a stacked mixer and VCO architecture, and variable-gain baseband amplifiers (VGA). Current-reused techniques, by sharing gain stages and stacked components, are explored in the receiver design for the further reduction of power consumption. The prototype chip, which was fabricated in a 0.18 mu m CMOS process, occupies a chip area of 3.67mm(2), including pads and impedance matching networks. At the 2.4GHz band, the proposed receiver achieves a maximum gain of 43dB, a noise figure of 8.9dB, and a 1-dB compression point (P1dB) larger than -34dBm. At the 5.2GHz band, the proposed receiver achieves a maximum gain of 31dB, a noise figure of 16.3dB, and a P1dB larger than -27dBm. The total power consumption is 7.3mW at a supply voltage of 1.2V. |
URI: | http://hdl.handle.net/11536/134369 |
ISBN: | 978-1-4799-5341-7 |
ISSN: | 0271-4302 |
期刊: | 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 1398 |
結束頁: | 1401 |
Appears in Collections: | Conferences Paper |