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dc.contributor.authorLiu, Chun-Yien_US
dc.contributor.authorSie, Meng-Siouen_US
dc.contributor.authorLeong, Edmund Wen Jenen_US
dc.contributor.authorYao, Yu-Chengen_US
dc.contributor.authorJen, Chih-Weien_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2017-04-21T06:50:05Z-
dc.date.available2017-04-21T06:50:05Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4799-5341-7en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/134374-
dc.description.abstractIn this paper, a novel memory access reordering polyphase network (PPN) for 60 GHz filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver is presented. The 8X-parallelism architecture of PPN is integrated into our 8X-parallelism digital baseband receiver. The PPN is designed based on IEEE 802.15.3c and IEEE 802.11ad standards. The PPN contains three key modules including memory bank, filter coefficient selector and 4-tap PPN filter. The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process. The implementation result shows it can operate at specified 330/500 MHz clock rate with power consumption of 17/26 mW at 0.81 V supply voltage. With 8X-parallelism architecture, the sampling rate supports up to 2.64/4 GHz.en_US
dc.language.isoen_USen_US
dc.titleA Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiveren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage2655en_US
dc.citation.epage2658en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000390094702203en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper