標題: | All Digital Phase-Locked Loop Using Active Inductor Oscillator and Novel Locking Algorithm |
作者: | Huang, Tzu-Chi Huang, Hong-Yi Liu, Jen-Chieh Cheng, Kuo-Hsing Luo, Ching-Hsing 電控工程研究所 Institute of Electrical and Control Engineering |
公開日期: | 2011 |
摘要: | A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390x390 um(2). The power consumption is 5.4 mW at 416 MHz. |
URI: | http://hdl.handle.net/11536/134394 |
ISBN: | 978-1-4244-9474-3 |
ISSN: | 0271-4302 |
期刊: | 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 486 |
結束頁: | 489 |
顯示於類別: | 會議論文 |