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dc.contributor.authorTseng, Chi-Yaoen_US
dc.contributor.authorWei, Ting-Chenen_US
dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorJon, Shyh-Jyeen_US
dc.date.accessioned2017-04-21T06:49:42Z-
dc.date.available2017-04-21T06:49:42Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0582-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/134456-
dc.description.abstractFrom hardware point of view, system and RTL low power and power aware design techniques are applied to the DVB-T/H baseband inner receiver. In RTL design, we use pre-computation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture so that each block can reduce power from 3% to 26%. In system level, the proposed DPM (Dynamic Power Manager) is a power control unit or our system. When the system enters the offset tracking mode, the DPM controls the power states of system blocks between the GI (Guard Interval) period and symbol period. The power reduction ratio ranges from 3%-20% (it depends on the GI mode). Moreover, a predicted phase scheme is proposed to provide the initial phase offset for the start of symbol period during offset tracking mode. The overall reduction for synchronization loop is about 50% in both hardware area and power.en_US
dc.language.isoen_USen_US
dc.titleLow power and power aware design for DVB-T/H baseband inner receiveren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage204en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000247000000051en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper