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dc.contributor.authorLin, Jian-Heen_US
dc.contributor.authorTsou, Wen-Jieen_US
dc.contributor.authorChen, Ke-Horngen_US
dc.contributor.authorWey, Chin-Longen_US
dc.contributor.authorLin, Ying-Hsien_US
dc.contributor.authorLin, Jian-Ruen_US
dc.contributor.authorTsai, Tsung-Yenen_US
dc.date.accessioned2017-04-21T06:49:31Z-
dc.date.available2017-04-21T06:49:31Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-5090-1570-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/134522-
dc.description.abstractconventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18 mu m CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.en_US
dc.language.isoen_USen_US
dc.subjectdigital low-dropout-regulator (DLDO)en_US
dc.subjectsteady-state load current (SLC)en_US
dc.subjectdynamic gain scaling (DGS)en_US
dc.titleA Digital Low-Dropout-Regulator with Steady-State Load Current (SLC) Estimator and Dynamic Gain Scaling (DGS) Controlen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)en_US
dc.citation.spage37en_US
dc.citation.epage40en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000392651200010en_US
dc.citation.woscount0en_US
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