標題: A Fully-Integrated Ka-Band 4TX/4RX Phased-Array Transceiver IC in 65nm CMOS
作者: Chu, Ching-Yun
Tseng, Shao-Ting
Gao, Jing-Zhi
Chen, Yuan-Pu
Chang, Yu-Chen
Tseng, Chien-Wei
Huang, Tzu-Yuan
Hu, Bo-Syun
Su, Borching
Chu, Ta-Shun
Wang, Yu-Jiu
交大名義發表
National Chiao Tung University
關鍵字: CMOS;Ka-Band;phased-array
公開日期: 2016
摘要: This paper presents a fully-integrated Ka-band 4RX/4TX phased-array transceiver IC. The four transceiver channels are synchronized by an I/Q standing wave oscillator (SWO). Their signal phases are shifted by hybrid analog IF and LO phase interpolators, and can be controlled digitally and independently. The SWO further composes an on-chip PLL, and is locked to a 1.09 GHz off-chip global reference to scale to a large array at board level. Each receiver channel achieves 66 dB maximum conversion gain and 4.4 dB minimum noise figure. Each transmitter channel achieves 18 dBm maximum output power. The chip is mounted on a high-frequency laminate, inside which embedded cables connect its RF pads to Vivaldi antennas also inside the same PCB. With the PCB, each channel achieves 360 degrees phase shifting capability under a maximum calibrated 3.7 degrees phase errors. The PCB module presents successful beam steering with 23 degrees measured four-channel 3-dB beamwidth. This chip consumes a peak 5 W power at transmit mode, and is fabricated in TSMC 65nm CMOS technology with a 4 x 2.5 mm(2) chip area.
URI: http://hdl.handle.net/11536/134528
ISBN: 978-1-5090-1235-0
期刊: 2016 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT)
顯示於類別:會議論文