完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Du, Yuan | en_US |
dc.contributor.author | Cho, Wei-Han | en_US |
dc.contributor.author | Li, Yilei | en_US |
dc.contributor.author | Wong, Chien-Heng | en_US |
dc.contributor.author | Du, Jieqiong | en_US |
dc.contributor.author | Huang, Po-Tsang | en_US |
dc.contributor.author | Kim, Yanghyo | en_US |
dc.contributor.author | Chen, Zuow-Zun | en_US |
dc.contributor.author | Lee, Sheau Jiung | en_US |
dc.contributor.author | Chang, Mau-Chung Frank | en_US |
dc.date.accessioned | 2017-04-21T06:49:21Z | - |
dc.date.available | 2017-04-21T06:49:21Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-5090-0635-9 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134571 | - |
dc.description.abstract | A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm(2) in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 mu W/Gb/s/dB considering channel condition. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 16Gb/s 14.7mW Tri-Band Cognitive Serial Link Transmitter with Forwarded Clock to Enable PAM-16 / 256-QAM and Channel Response Detection in 28 nm CMOS | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS) | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000392504700066 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |