Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Juang, Tso-Bing | en_US |
dc.contributor.author | Lee, Ying-Ren | en_US |
dc.contributor.author | Chiu, Chin-Chieh | en_US |
dc.date.accessioned | 2017-04-21T06:49:19Z | - |
dc.date.available | 2017-04-21T06:49:19Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-5090-3219-8 | en_US |
dc.identifier.issn | 2163-9612 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134585 | - |
dc.description.abstract | In this paper, low-cost concurrent error detection (CED) schemes for logarithmic converters are proposed. By adopting our previously proposed logarithmic converters with developed converters with the same functions, the proposed schemes can perform logarithmic conversion with CED ability. Simulation results show that our proposed CED schemes for logarithmic converters can achieve at most 61.65% area and 32% delay reductions. Our proposed low-cost CED schemes can be applied to real-time computation-intensive computations for achieving high-speed logarithmic conversions with CED ability. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Concurrent error detection (CED) | en_US |
dc.subject | logarithmic number system (LNS) | en_US |
dc.subject | computer arithmetic | en_US |
dc.subject | VLSI design | en_US |
dc.title | Low-Cost Concurrent Error Detection Schemes for Logarithmic Converters | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | en_US |
dc.citation.spage | 213 | en_US |
dc.citation.epage | 214 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000392251200104 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |