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dc.contributor.authorJuang, Tso-Bingen_US
dc.contributor.authorLee, Ying-Renen_US
dc.contributor.authorChiu, Chin-Chiehen_US
dc.date.accessioned2017-04-21T06:49:19Z-
dc.date.available2017-04-21T06:49:19Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-5090-3219-8en_US
dc.identifier.issn2163-9612en_US
dc.identifier.urihttp://hdl.handle.net/11536/134585-
dc.description.abstractIn this paper, low-cost concurrent error detection (CED) schemes for logarithmic converters are proposed. By adopting our previously proposed logarithmic converters with developed converters with the same functions, the proposed schemes can perform logarithmic conversion with CED ability. Simulation results show that our proposed CED schemes for logarithmic converters can achieve at most 61.65% area and 32% delay reductions. Our proposed low-cost CED schemes can be applied to real-time computation-intensive computations for achieving high-speed logarithmic conversions with CED ability.en_US
dc.language.isoen_USen_US
dc.subjectConcurrent error detection (CED)en_US
dc.subjectlogarithmic number system (LNS)en_US
dc.subjectcomputer arithmeticen_US
dc.subjectVLSI designen_US
dc.titleLow-Cost Concurrent Error Detection Schemes for Logarithmic Convertersen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)en_US
dc.citation.spage213en_US
dc.citation.epage214en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000392251200104en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper