標題: | Low-Cost Concurrent Error Detection Schemes for Logarithmic Converters |
作者: | Juang, Tso-Bing Lee, Ying-Ren Chiu, Chin-Chieh 資訊工程學系 Department of Computer Science |
關鍵字: | Concurrent error detection (CED);logarithmic number system (LNS);computer arithmetic;VLSI design |
公開日期: | 2016 |
摘要: | In this paper, low-cost concurrent error detection (CED) schemes for logarithmic converters are proposed. By adopting our previously proposed logarithmic converters with developed converters with the same functions, the proposed schemes can perform logarithmic conversion with CED ability. Simulation results show that our proposed CED schemes for logarithmic converters can achieve at most 61.65% area and 32% delay reductions. Our proposed low-cost CED schemes can be applied to real-time computation-intensive computations for achieving high-speed logarithmic conversions with CED ability. |
URI: | http://hdl.handle.net/11536/134585 |
ISBN: | 978-1-5090-3219-8 |
ISSN: | 2163-9612 |
期刊: | 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) |
起始頁: | 213 |
結束頁: | 214 |
Appears in Collections: | Conferences Paper |