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dc.contributor.authorChiu, Yu-Chienen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.authorHsu, Hsiao-Hsuanen_US
dc.contributor.authorCheng, Chun-Huen_US
dc.contributor.authorLee, Min-Hungen_US
dc.date.accessioned2017-04-21T06:49:01Z-
dc.date.available2017-04-21T06:49:01Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-7362-3en_US
dc.identifier.issn1541-7026en_US
dc.identifier.urihttp://hdl.handle.net/11536/134590-
dc.description.abstractWe demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 10(12)-cycling endurance at 85 degrees C. Such excellent endurance reliability at 85 degrees C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.en_US
dc.language.isoen_USen_US
dc.subjectnonvolatile memoryen_US
dc.subjectferroelectric polarizationen_US
dc.subjectcharge trappingen_US
dc.subjectenduranceen_US
dc.subjectretentionen_US
dc.titleImpact of Nanoscale Polarization Relaxation on Endurance Reliability of One-Transistor Hybrid Memory Using Combined Storage Mechanismsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000371888900150en_US
dc.citation.woscount0en_US
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