Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chou, Yu-Che | en_US |
dc.contributor.author | Hsu, Chung-Chun | en_US |
dc.contributor.author | Chun, Cheng-Ting | en_US |
dc.contributor.author | Chou, Chen-Han | en_US |
dc.contributor.author | Tsai, Ming-Li | en_US |
dc.contributor.author | Tsai, Yi-He | en_US |
dc.contributor.author | Lee, Wei-Li | en_US |
dc.contributor.author | Wang, Shin-Yuan | en_US |
dc.contributor.author | Luo, Guang-Li | en_US |
dc.contributor.author | Chien, Chao-Hsin | en_US |
dc.date.accessioned | 2017-04-21T06:48:50Z | - |
dc.date.available | 2017-04-21T06:48:50Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-5090-1493-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134636 | - |
dc.description.abstract | In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I-ON/I-OFF ratio and lower junction leakage (4x10(-3)mu A/cm(2)). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6x10(-6)mu A/cm(2))as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I-ON/I-OFF ratio similar to 8x10(3) (I-S) than the conventional Ge FinFET (I-ON/I-OFF similar to 2x10 (3)). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Body-tied Ge FinFET | en_US |
dc.subject | DIBL (drain-induced barrier lowering) | en_US |
dc.subject | implantation | en_US |
dc.subject | retrograde-well | en_US |
dc.title | Integration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantation | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | en_US |
dc.citation.spage | 142 | en_US |
dc.citation.epage | 144 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000391840000041 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |