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dc.contributor.authorChou, Yu-Cheen_US
dc.contributor.authorHsu, Chung-Chunen_US
dc.contributor.authorChun, Cheng-Tingen_US
dc.contributor.authorChou, Chen-Hanen_US
dc.contributor.authorTsai, Ming-Lien_US
dc.contributor.authorTsai, Yi-Heen_US
dc.contributor.authorLee, Wei-Lien_US
dc.contributor.authorWang, Shin-Yuanen_US
dc.contributor.authorLuo, Guang-Lien_US
dc.contributor.authorChien, Chao-Hsinen_US
dc.date.accessioned2017-04-21T06:48:50Z-
dc.date.available2017-04-21T06:48:50Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-5090-1493-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/134636-
dc.description.abstractIn this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I-ON/I-OFF ratio and lower junction leakage (4x10(-3)mu A/cm(2)). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6x10(-6)mu A/cm(2))as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I-ON/I-OFF ratio similar to 8x10(3) (I-S) than the conventional Ge FinFET (I-ON/I-OFF similar to 2x10 (3)).en_US
dc.language.isoen_USen_US
dc.subjectBody-tied Ge FinFETen_US
dc.subjectDIBL (drain-induced barrier lowering)en_US
dc.subjectimplantationen_US
dc.subjectretrograde-wellen_US
dc.titleIntegration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)en_US
dc.citation.spage142en_US
dc.citation.epage144en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000391840000041en_US
dc.citation.woscount0en_US
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