Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kuo, Ming-Hao | en_US |
dc.contributor.author | Lee, M. C. | en_US |
dc.contributor.author | Tien, J. W. | en_US |
dc.contributor.author | Lai, Wei-Ting | en_US |
dc.contributor.author | Li, Pei-Wen | en_US |
dc.date.accessioned | 2017-04-21T06:48:48Z | - |
dc.date.available | 2017-04-21T06:48:48Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-5090-0726-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134684 | - |
dc.description.abstract | Ge-dot/SiO2/SiGe-channel photoMOSFETs are demonstrated on a Si-photonics platform. The photoMOSFET is fabricated in standard CMOS processes with a self-organized gate stack of Ge-dot/SiO2/SiGe-channel using thermal oxidation of SiGe nanopillars over Si3N4 layers on Si substrates. The Ge-dot photoMOSFET, with 3 mu m channel length and 70 mu m channel width, features responsivity of over 2000A/W and 100 A/W with 6pW and 0.2 mu W, respectively, under illumination at 850nm. The responsivity is further improved by reducing the dot size and increasing the spatial density and most importantly, is insensitive to the gate oxide thickness, which is a great benefit for reducing the input capacitance and thus, improving speed and power consumption. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Optimal design of Ge-dot photoMOSFETs for highly-integrated monolithic Si Photonics | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) | en_US |
dc.citation.spage | 212 | en_US |
dc.citation.epage | 213 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000391250500093 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |