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dc.contributor.authorLiao, Chien-Huien_US
dc.contributor.authorWen, Charles H. -P.en_US
dc.contributor.authorChakrabarty, Krishnenduen_US
dc.date.accessioned2017-04-21T06:48:48Z-
dc.date.available2017-04-21T06:48:48Z-
dc.date.issued2015en_US
dc.identifier.isbn978-3-9815-3704-8en_US
dc.identifier.issn1530-1591en_US
dc.identifier.urihttp://hdl.handle.net/11536/134691-
dc.description.abstractHotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to more dynamic voltage and frequency scaling (DVFS), resulting in degraded throughput. Therefore, a new thermal-constrained task scheduler based on thermal-pattern-aware voltage assignment (TPAVA) is proposed in this paper. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. Moreover, the proposed task scheduler integrates a vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs. Experimental results show that, compared with two previous methods, the proposed task scheduler can respectively lower hotspot occurrences by 47.13% and 53.91%, and improve throughput by 6.50% and 32.06%. As a result, TPAVA and VGVS are effectively for reducing occurrences of hotspots and optimizing throughput for 3D-MCPs under thermal constraints.en_US
dc.language.isoen_USen_US
dc.titleAn Online Thermal-Constrained Task Scheduler for 3D Multi-Core Processorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)en_US
dc.citation.spage351en_US
dc.citation.epage356en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000380393200065en_US
dc.citation.woscount1en_US
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