完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Hung-Wen | en_US |
dc.contributor.author | Ho, Ying-Chieh | en_US |
dc.contributor.author | Fa, YingLin | en_US |
dc.contributor.author | Su, ChauChin | en_US |
dc.date.accessioned | 2017-04-21T06:49:54Z | - |
dc.date.available | 2017-04-21T06:49:54Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-5309-2 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134853 | - |
dc.description.abstract | This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm(2). At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 5Gb/s Pulse Signaling Interface for Low Power On-Chip Data Communication | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | en_US |
dc.citation.spage | 201 | en_US |
dc.citation.epage | 204 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000287216000051 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |