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dc.contributor.authorLin, Hung-Wenen_US
dc.contributor.authorHo, Ying-Chiehen_US
dc.contributor.authorFa, YingLinen_US
dc.contributor.authorSu, ChauChinen_US
dc.date.accessioned2017-04-21T06:49:54Z-
dc.date.available2017-04-21T06:49:54Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-5309-2en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/134853-
dc.description.abstractThis paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm(2). At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm.en_US
dc.language.isoen_USen_US
dc.titleA 5Gb/s Pulse Signaling Interface for Low Power On-Chip Data Communicationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage201en_US
dc.citation.epage204en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000287216000051en_US
dc.citation.woscount0en_US
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