Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yeh, Chih-Ting | en_US |
dc.contributor.author | Liang, Yung-Chih | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.date.accessioned | 2017-04-21T06:49:53Z | - |
dc.date.available | 2017-04-21T06:49:53Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-5271-2 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134862 | - |
dc.description.abstract | The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | en_US |
dc.citation.spage | 241 | en_US |
dc.citation.epage | 244 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000300486600060 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |