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dc.contributor.authorShen, Bor-Yehen_US
dc.contributor.authorHsu, Wei Chungen_US
dc.contributor.authorYang, Wuuen_US
dc.date.accessioned2017-04-21T06:49:52Z-
dc.date.available2017-04-21T06:49:52Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-934272-91-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/134873-
dc.description.abstractCode size is an important issue in many embedded systems. In order to reduce code size, newer embedded RISC processors employ a mixed-width instruction set, where processor architectures support interleaved execution between normal (usually 32-bit) and narrow (usually 16-bit) instructions without explicit mode switch. However, because of the restriction of the encoding length, narrow instructions can only access a limited set of registers. Therefore, for a mixed-width instruction set, proper register allocation can reduce code size. One approach is to re-assign the registers after traditional register allocation. In this paper, we prove that this register reassignment problem is NP-complete by showing that the 0-1 knapsack problem is a special case of this problem. We also propose a method for register reassignment for a mixed-width instruction set with the main goal of code size reduction.en_US
dc.language.isoen_USen_US
dc.subjectMixed-width ISAen_US
dc.subjectCode Size Reductionen_US
dc.subjectRegister Reassignmenten_US
dc.subjectThumb-2en_US
dc.subjectKnapsack Problemen_US
dc.subjectNP-completeen_US
dc.titleRegister Reassignment for Mixed-width ISAs is an NP-Complete Problemen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIMCIC 2010: INTERNATIONAL MULTI-CONFERENCE ON COMPLEXITY, INFORMATICS AND CYBERNETICS, VOL I (POST-CONFERENCE EDITION)en_US
dc.citation.spage139en_US
dc.citation.epage143en_US
dc.contributor.department资讯工程学系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000391415900025en_US
dc.citation.woscount0en_US
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