標題: Portable simulation/emulation stimulus on an industrial-strength SoC
作者: Torres, Francisco
Srivastava, Rohit
Ruiz, Javier
Wen, H. -P.
Bose, Mrinal
Bhadra, Jayanta
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture (TM) Technology-based SoC demonstrate about a 100x speedup on the emulator vis-a-vis the simulator.
URI: http://hdl.handle.net/11536/134995
ISBN: 978-1-4244-4868-5
ISSN: 1089-3539
期刊: ITC: 2009 INTERNATIONAL TEST CONFERENCE
起始頁: 623
結束頁: 623
顯示於類別:會議論文