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dc.contributor.authorYan, Jin-Taien_US
dc.contributor.authorChen, Zhi-Weien_US
dc.contributor.authorChiang, Bo-Yien_US
dc.contributor.authorLee, Yu-Minen_US
dc.date.accessioned2017-04-21T06:49:38Z-
dc.date.available2017-04-21T06:49:38Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2341-5en_US
dc.identifier.urihttp://dx.doi.org/10.1109/APCCAS.2008.4746363en_US
dc.identifier.urihttp://hdl.handle.net/11536/135038-
dc.description.abstractIn this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.en_US
dc.language.isoen_USen_US
dc.titleTiming-Constrained Yield-Driven Redundant Via Insertionen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/APCCAS.2008.4746363en_US
dc.identifier.journal2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4en_US
dc.citation.spage1688en_US
dc.citation.epage+en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000268007100418en_US
dc.citation.woscount1en_US
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