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dc.contributor.authorChiu, C. S.en_US
dc.contributor.authorChen, W. L.en_US
dc.contributor.authorLiao, K. H.en_US
dc.contributor.authorChen, B. Y.en_US
dc.contributor.authorTeng, Y. M.en_US
dc.contributor.authorHuang, G. W.en_US
dc.contributor.authorWu, L. K.en_US
dc.date.accessioned2017-04-21T06:49:37Z-
dc.date.available2017-04-21T06:49:37Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2866-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/135055-
dc.description.abstractThe pad structure of CMOS technology is characterized by way of time domain reflectometry measurement. Using the on-wafer TDR measurement system, the capacitance of the pad in the CMOS process was extracted and estimated. Measured and Simulated TDR data are also presented in this study. The capacitance is estimated when the curve is fitted by mathematical tool. This method is simple to use, and furthermore the results agree with data extracted from vector network analyzer.en_US
dc.language.isoen_USen_US
dc.subjectTime domain reflectometry (TDR)en_US
dc.subjectCapacitanceen_US
dc.subjectImpedanceen_US
dc.subjectPad structureen_US
dc.subjectOn-waferen_US
dc.titlePad Characterization for CMOS Technology Using Time Domain Reflectometryen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2008 IEEE INTERNATIONAL RF AND MICROWAVE CONFERENCE, PROCEEDINGSen_US
dc.citation.spage214en_US
dc.citation.epage+en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000268637900049en_US
dc.citation.woscount0en_US
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