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dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorHwang, Jiunn-Renen_US
dc.contributor.authorLi, Yimingen_US
dc.contributor.authorYang, Fu-Liangen_US
dc.date.accessioned2017-04-21T06:49:09Z-
dc.date.available2017-04-21T06:49:09Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0584-8en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ISPACS.2007.4445828en_US
dc.identifier.urihttp://hdl.handle.net/11536/135148-
dc.description.abstractSTI stress buffer techniques including sidewall stress buffer and channel surface buffer layers are developed to reduce the impact of compressive STI stress on the mobility of advanced N-MOS devices. For L-g down to 35nm, 7% improvement of drive current at N-MOS has been achieved, while no degradation at P-MOS drive current and maintaining the same junction leakage at both N-MOS and P-MOS. A stress relaxation model with simulation is proposed to account for the enhanced transportation characteristics.en_US
dc.language.isoen_USen_US
dc.titleNovel strained CMOS devices with STI stress buffer layersen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ISPACS.2007.4445828en_US
dc.identifier.journal2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage80en_US
dc.citation.epage+en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000247059300036en_US
dc.citation.woscount0en_US
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