標題: iTimerC: Common Path Pessimism Removal Using Effective Reduction Methods
作者: Yang, Yu-Ming
Chang, Yu-Wei
Jiang, Iris Hui-Ru
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: static timing analysis;common path pessimism removal;on-chip variations;branch-and-bound
公開日期: 2014
摘要: Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this paper, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, and dynamic bounding. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.
URI: http://hdl.handle.net/11536/135326
ISBN: 978-1-4799-6278-5
ISSN: 1933-7760
期刊: 2014 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)
起始頁: 600
結束頁: 605
Appears in Collections:Conferences Paper