完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hung, C. M. | en_US |
dc.contributor.author | Li, K. C. | en_US |
dc.contributor.author | Hsieh, E. R. | en_US |
dc.contributor.author | Wang, C. T. | en_US |
dc.contributor.author | Kou, C. I. | en_US |
dc.contributor.author | Chang, Edward Y. | en_US |
dc.contributor.author | Chung, Steve S. | en_US |
dc.date.accessioned | 2017-04-21T06:50:15Z | - |
dc.date.available | 2017-04-21T06:50:15Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.isbn | 978-1-4799-5677-7 | en_US |
dc.identifier.issn | 2161-4636 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135337 | - |
dc.description.abstract | HEMT suffers from parasitic resistance (R-sd) and capacitance(C-gd) effects with the shrinking of channel length, leading to degraded performance in logic and RF applications. A new while simple method to extract parasitic RC has been proposed to construct accurate transport parameters in HEMTs. In comparison to the constant-R-sd method, this new voltage dependent method provides more convincing results, especially for very short channel devices. On the other hand, an accurate C-gd correction method has also been incorporated to adequately represent the mobility. Finally, a guideline to design high performance HEMTs has been proposed. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000393376800093 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |