完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHung, C. M.en_US
dc.contributor.authorLi, K. C.en_US
dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorWang, C. T.en_US
dc.contributor.authorKou, C. I.en_US
dc.contributor.authorChang, Edward Y.en_US
dc.contributor.authorChung, Steve S.en_US
dc.date.accessioned2017-04-21T06:50:15Z-
dc.date.available2017-04-21T06:50:15Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-5677-7en_US
dc.identifier.issn2161-4636en_US
dc.identifier.urihttp://hdl.handle.net/11536/135337-
dc.description.abstractHEMT suffers from parasitic resistance (R-sd) and capacitance(C-gd) effects with the shrinking of channel length, leading to degraded performance in logic and RF applications. A new while simple method to extract parasitic RC has been proposed to construct accurate transport parameters in HEMTs. In comparison to the constant-R-sd method, this new voltage dependent method provides more convincing results, especially for very short channel devices. On the other hand, an accurate C-gd correction method has also been incorporated to adequately represent the mobility. Finally, a guideline to design high performance HEMTs has been proposed.en_US
dc.language.isoen_USen_US
dc.titleA Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effectsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW)en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000393376800093en_US
dc.citation.woscount0en_US
顯示於類別:會議論文