完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chung, Steve | en_US |
dc.date.accessioned | 2017-04-21T06:49:30Z | - |
dc.date.available | 2017-04-21T06:49:30Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-8364-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135769 | - |
dc.description.abstract | The breakdown path induced by BTI stress in a MOSFET device can he traced from the experiment. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path, i.e., from the leakage by measuring the Ig current as a function of time, It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths will be presented. The soft-breakdown path is in a shape like spindle, while the hard breakdown behaves like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Leakage path | en_US |
dc.subject | high-k | en_US |
dc.subject | BTI | en_US |
dc.subject | soft-breakdown | en_US |
dc.subject | hard breakdown | en_US |
dc.subject | TDDB lifetime | en_US |
dc.title | The Path Finding of Gate Dielectric Breakdown in Advanced High-k Metal-Gate CMOS Devices | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | en_US |
dc.citation.spage | 360 | en_US |
dc.citation.epage | 364 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380458700091 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |