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dc.contributor.authorYang, Hao-Yuen_US
dc.contributor.authorKuo, Shih-Huaen_US
dc.contributor.authorHuang, Tzu-Hsuanen_US
dc.contributor.authorChen, Chi-Hungen_US
dc.contributor.authorLin, Chrisen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.date.accessioned2017-04-21T06:49:25Z-
dc.date.available2017-04-21T06:49:25Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-7597-6en_US
dc.identifier.issn1093-0167en_US
dc.identifier.urihttp://hdl.handle.net/11536/135805-
dc.description.abstractDue to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.en_US
dc.language.isoen_USen_US
dc.titleRandom Pattern Generation for Post-Silicon Validation of DDR3 SDRAMen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE 33RD VLSI TEST SYMPOSIUM (VTS)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380437500035en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper