完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lai, Wei-Ting | en_US |
dc.contributor.author | Yang, Kuo-Ching | en_US |
dc.contributor.author | Liao, Po-Hsiang | en_US |
dc.contributor.author | George, Thomas | en_US |
dc.contributor.author | Li, Pei-Wen | en_US |
dc.date.accessioned | 2017-04-21T06:49:45Z | - |
dc.date.available | 2017-04-21T06:49:45Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4673-7604-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135839 | - |
dc.description.abstract | We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGechannel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Genanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5x10(11) cm(-2)eV(-1), which is beneficial for advanced Ge MOS applications. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 SILICON NANOELECTRONICS WORKSHOP (SNW) | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000380461900008 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |