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dc.contributor.authorLai, Wei-Tingen_US
dc.contributor.authorYang, Kuo-Chingen_US
dc.contributor.authorLiao, Po-Hsiangen_US
dc.contributor.authorGeorge, Thomasen_US
dc.contributor.authorLi, Pei-Wenen_US
dc.date.accessioned2017-04-21T06:49:45Z-
dc.date.available2017-04-21T06:49:45Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-7604-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/135839-
dc.description.abstractWe reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGechannel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Genanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5x10(11) cm(-2)eV(-1), which is beneficial for advanced Ge MOS applications.en_US
dc.language.isoen_USen_US
dc.titleGate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 SILICON NANOELECTRONICS WORKSHOP (SNW)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000380461900008en_US
dc.citation.woscount0en_US
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