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dc.contributor.authorWu, Wei-Hsuanen_US
dc.contributor.authorSun, Wei-Chengen_US
dc.contributor.authorYang, Chia-Hsiangen_US
dc.contributor.authorUeng, Yeong-Luhen_US
dc.date.accessioned2017-04-21T06:49:12Z-
dc.date.available2017-04-21T06:49:12Z-
dc.date.issued2015en_US
dc.identifier.isbn978-4-86348-502-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/135885-
dc.description.abstractA low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm(2) in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4x4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO detectors and LDPC decoders, this work achieves even higher area and energy efficiencies, despite the improved error performance.en_US
dc.language.isoen_USen_US
dc.titleA 794Mbps 135mW Iterative Detection and Decoding Receiver for 4x4 LDPC-Coded MIMO Systems in 40nmen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000370961400034en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper