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dc.contributor.authorSu, P. C.en_US
dc.contributor.authorChung, Y. T.en_US
dc.contributor.authorChen, M. C.en_US
dc.contributor.authorWang, Tahuien_US
dc.date.accessioned2017-04-21T06:48:58Z-
dc.date.available2017-04-21T06:48:58Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4673-8833-7en_US
dc.identifier.issn2330-7978en_US
dc.identifier.urihttp://hdl.handle.net/11536/135897-
dc.description.abstractFactors affecting SET-disturb failure time (tau(f)) in a tungsten oxide resistive switching memory including SET/RESET cycling stress, resistance window in operation and SET-disturb voltage are investigated. A SET-disturb failure time in high resistance state (HRS) may degrade by orders of magnitude in a post-cycling cell. The degradation is attributed to the formation of a current percolation path of cycling stress-generated traps. A one-dimensional percolation model is proposed for the tau(f) degradation. The dependence of tau(f) on resistance window in operation is characterized. We find that tau(f) is greatly affected by the current level of LRS. The strong LRS dependence of tf is attributed to a small Weibull slope of tau(f). In addition, we perform statistical characterizations of tau(f) at different SET-disturb voltages. A relationship between tau(f) and a SET-disturb voltage in a stressed cell is given.en_US
dc.language.isoen_USen_US
dc.subjectRRAMen_US
dc.subjectSET-disturb failure timeen_US
dc.subjectcycling stressen_US
dc.subjectresistance windowen_US
dc.subjectSET-disturb voltageen_US
dc.titleInvestigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memoryen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000382530600031en_US
dc.citation.woscount0en_US
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