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dc.contributor.authorChen, Chieh-Yangen_US
dc.contributor.authorHuang, Wen-Tsungen_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2017-04-21T06:49:20Z-
dc.date.available2017-04-21T06:49:20Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-7581-5en_US
dc.identifier.issn1948-3287en_US
dc.identifier.urihttp://hdl.handle.net/11536/135975-
dc.description.abstractIn this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. The resist-LER is most influential on characteristic fluctuation. For the same type, spacer-LER has at least 85 % improvement on sigma V-th compared with resist-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.en_US
dc.language.isoen_USen_US
dc.subjectLine edge roughnessen_US
dc.subjectfin-en_US
dc.subjectresist-en_US
dc.subjectspacer-en_US
dc.subjectsidewall-en_US
dc.subjectgate-LERen_US
dc.subjecttrapezoidal bulk FinFETen_US
dc.subjectdigital circuiten_US
dc.titleElectrical Characteristic and Power Consumption Fluctuations of Trapezoidal Bulk FinFET Devices and Circuits Induced by Random Line Edge Roughnessen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)en_US
dc.citation.spage61en_US
dc.citation.epage64en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000380456100011en_US
dc.citation.woscount2en_US
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