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dc.contributor.authorLin, Chun-Yuen_US
dc.contributor.authorChang, Pin-Hsinen_US
dc.contributor.authorChang, Rong-Kunen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorWang, Wen-Taien_US
dc.date.accessioned2017-04-21T06:49:20Z-
dc.date.available2017-04-21T06:49:20Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-9928-6en_US
dc.identifier.issn1946-1550en_US
dc.identifier.urihttp://hdl.handle.net/11536/135977-
dc.description.abstractA vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.en_US
dc.language.isoen_USen_US
dc.titleVertical SCR Structure for On-Chip ESD Protection in Nanoscale CMOS Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015)en_US
dc.citation.spage255en_US
dc.citation.epage258en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380466200065en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper