Vertical SCR Structure for On-Chip ESD Protection in Nanoscale CMOS Technology

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, Chun-Yu	en_US
dc.contributor.author	Chang, Pin-Hsin	en_US
dc.contributor.author	Chang, Rong-Kun	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Wang, Wen-Tai	en_US
dc.date.accessioned	2017-04-21T06:49:20Z	-
dc.date.available	2017-04-21T06:49:20Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-4799-9928-6	en_US
dc.identifier.issn	1946-1550	en_US
dc.identifier.uri	http://hdl.handle.net/11536/135977	-
dc.description.abstract	A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.	en_US
dc.language.iso	en_US	en_US
dc.title	Vertical SCR Structure for On-Chip ESD Protection in Nanoscale CMOS Technology	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015)	en_US
dc.citation.spage	255	en_US
dc.citation.epage	258	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000380466200065	en_US
dc.citation.woscount	0	en_US
顯示於類別：	會議論文