標題: Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85 degrees C-Extrapolated 10(16) Endurance
作者: Chiu, Yu-Chien
Cheng, Chun-Hu
Chang, Chun-Yen
Lee, Min-Hung
Hsu, Hsiao-Hsuan
Yen, Shiang-Shiou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2015
摘要: In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10(-15) A/mu m at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large Delta V-T window of 2.8V, fast 20-ns speed, 10(3)s retention at 85 degrees C, and long extrapolated 10(16) endurance at 85 degrees C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.
URI: http://hdl.handle.net/11536/135996
ISBN: 978-4-86348-501-3
期刊: 2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY)
Appears in Collections:Conferences Paper