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dc.contributor.authorLuo, Qingen_US
dc.contributor.authorXu, Xiaoxinen_US
dc.contributor.authorLiu, Hongtaoen_US
dc.contributor.authorLv, Hangbingen_US
dc.contributor.authorGong, Tianchengen_US
dc.contributor.authorLong, Shibingen_US
dc.contributor.authorLiu, Qien_US
dc.contributor.authorSun, Haitaoen_US
dc.contributor.authorBanerjee, Writamen_US
dc.contributor.authorLi, Lingen_US
dc.contributor.authorGao, Jianfengen_US
dc.contributor.authorLu, Nianduanen_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorLi, Jingen_US
dc.contributor.authorLiu, Mingen_US
dc.date.accessioned2017-04-21T06:48:32Z-
dc.date.available2017-04-21T06:48:32Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9894-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/136041-
dc.description.abstractDeveloping high performance self-selective cell (SSC) is one of the most critical issues of the integration of 3D vertical RRAM (V-RRAM). In this work, a four-layer V-RRAM array, with high performance HfO2/mixed ionic and electronic conductor (MIEC) bilayer SSC, was demonstrated for the first time. Several salient features were achieved, including ultra-low half-select leakage (<0.1 pA), very high nonlinearity (>10(3)), low operation current (nA level), self-compliance, high endurance (>10(7)), and robust read/write disturbance immunity.en_US
dc.language.isoen_USen_US
dc.titleDemonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cellsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380472500061en_US
dc.citation.woscount0en_US
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