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dc.contributor.authorHuang, Chien_US
dc.contributor.authorHung, Tao-Yien_US
dc.contributor.authorWang, Pei-Yuen_US
dc.contributor.authorTsui, Bing-Yueen_US
dc.date.accessioned2017-04-21T06:48:34Z-
dc.date.available2017-04-21T06:48:34Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-4208-4en_US
dc.identifier.issn2378-8593en_US
dc.identifier.urihttp://hdl.handle.net/11536/136061-
dc.description.abstractTunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.en_US
dc.language.isoen_USen_US
dc.subjecttunnel field-effect transistoren_US
dc.subjectsubthreshold swingen_US
dc.subjectparasitic capacitanceen_US
dc.titleEvaluation of Electrical Performance of Various Tunnel TFETsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 International Symposium on Next-Generation Electronics (ISNE)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380530500090en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper


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