Evaluation of Electrical Performance of Various Tunnel TFETs

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DC 欄位	值	語言
dc.contributor.author	Huang, Chi	en_US
dc.contributor.author	Hung, Tao-Yi	en_US
dc.contributor.author	Wang, Pei-Yu	en_US
dc.contributor.author	Tsui, Bing-Yue	en_US
dc.date.accessioned	2017-04-21T06:48:34Z	-
dc.date.available	2017-04-21T06:48:34Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-4799-4208-4	en_US
dc.identifier.issn	2378-8593	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136061	-
dc.description.abstract	Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.	en_US
dc.language.iso	en_US	en_US
dc.subject	tunnel field-effect transistor	en_US
dc.subject	subthreshold swing	en_US
dc.subject	parasitic capacitance	en_US
dc.title	Evaluation of Electrical Performance of Various Tunnel TFETs	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2015 International Symposium on Next-Generation Electronics (ISNE)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000380530500090	en_US
dc.citation.woscount	0	en_US
顯示於類別：	會議論文