完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Xiao, An-Tia | en_US |
dc.contributor.author | Yang, Shiang-Ren | en_US |
dc.contributor.author | Miao, Yuan-Hsiang | en_US |
dc.contributor.author | Cheng, Ching-Hwa | en_US |
dc.contributor.author | Guo, Jiun-In | en_US |
dc.date.accessioned | 2017-04-21T06:48:29Z | - |
dc.date.available | 2017-04-21T06:48:29Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-6275-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136082 | - |
dc.description.abstract | Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage ( HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | multiple-voltage low power design | en_US |
dc.subject | H.264 encoder | en_US |
dc.subject | power-aware design | en_US |
dc.title | A Power-Aware Quad-Voltage H.264 Encoder Chip for Wireless Panoramic Endoscope Applications | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380584400044 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |