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dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorLu, P. Y.en_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorKe, J. C.en_US
dc.contributor.authorYang, C. W.en_US
dc.contributor.authorTsai, C. T.en_US
dc.contributor.authorYew, T. R.en_US
dc.date.accessioned2017-04-21T06:49:47Z-
dc.date.available2017-04-21T06:49:47Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-9928-6en_US
dc.identifier.issn1946-1550en_US
dc.identifier.urihttp://hdl.handle.net/11536/136100-
dc.description.abstractIn this paper, the evolution of BTI induced leakage paths has been evaluated by I-g-RTN technique and demonstrated on HK/MG CMOS devices. First, RTN measurement has been elaborated to identify the location of traps and their correlation to the leakage current. Then, the measured gate current transient can he used to analyze the formation of breakdown path. The results show that the evolution of leakage paths can be divided into three stages, i.e., (I) the early stage- only gate leakage and discrete RTN traps are observed, (2) the middle stage- the traps interacting with the percolation paths and exhibits a multi-level current variation, and (3) the last stage- the formation of breakdown path. These findings provide useful information on the understanding of gate dielectric breakdown in high-k CMOS devices.en_US
dc.language.isoen_USen_US
dc.titleThe RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015)en_US
dc.citation.spage154en_US
dc.citation.epage157en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380466200040en_US
dc.citation.woscount0en_US
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