A Delta Sigma TDC with Sub-ps Resolution for PLL Built-in Phase Noise Measurement

Abstract

A sub-ps Delta Sigma TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and Delta Sigma TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm(2).