標題: A Delta Sigma TDC with Sub-ps Resolution for PLL Built-in Phase Noise Measurement
作者: Chen, Wei-Zen
Kuo, Po-I
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: sub-ps Delta Sigma TDC;PLL;Phase Noise Measurement;BIST
公開日期: 2016
摘要: A sub-ps Delta Sigma TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and Delta Sigma TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm(2).
URI: http://hdl.handle.net/11536/136264
ISBN: 978-1-5090-2972-3
ISSN: 1930-8833
期刊: ESSCIRC CONFERENCE 2016
起始頁: 347
結束頁: 350
Appears in Collections:Conferences Paper