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dc.contributor.authorTsai, Chih-Yingen_US
dc.contributor.authorLee, Kao-Chien_US
dc.contributor.authorLin, Chien-Hsuehen_US
dc.contributor.authorYu, Sung-Chuen_US
dc.contributor.authorLiau, Wen-Rongen_US
dc.contributor.authorHou, Alex Chun-Liangen_US
dc.contributor.authorChen, Ying-Yenen_US
dc.contributor.authorKuo, Chun-Yien_US
dc.contributor.authorLee, Jih-Nungen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.date.accessioned2017-04-21T06:49:37Z-
dc.date.available2017-04-21T06:49:37Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4673-8454-4en_US
dc.identifier.issn1093-0167en_US
dc.identifier.urihttp://hdl.handle.net/11536/136267-
dc.description.abstractTo measure the variation of device V-t requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V-t for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V-t based on only the combined I-d measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of V-t mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of I-d measurement per DUT.en_US
dc.language.isoen_USen_US
dc.titlePredicting V-t Mean and Variance from Parallel I-d Measurement with Model-Fitting Techniqueen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE 34TH VLSI TEST SYMPOSIUM (VTS)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000386393800008en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper