標題: | A Multi-axis Readout Circuit using in Female Ovulation Monitoring platform |
作者: | Yu, Hsin-Yi Lai, Kelvin Yi-Tse Chang, Hsie-Chia Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Female Ovulation Monitoring Platform;Capacitive and Resistive Readout Circuits;Time-to-Digital Converter |
公開日期: | 2016 |
摘要: | In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18 mu m CMOSMEMS technology, the post-layout simulation results show that our circuit consumes 30 mu W and 49 mu W in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of dietemperature is 0 similar to 100 degrees C with 0.05 degrees C resolution. |
URI: | http://hdl.handle.net/11536/136391 |
ISBN: | 978-1-4673-9498-7 |
期刊: | 2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) |
顯示於類別: | 會議論文 |