3D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic Computation

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Wang, I-Ting	en_US
dc.contributor.author	Lin, Yen-Chuan	en_US
dc.contributor.author	Wang, Yu -Fen	en_US
dc.contributor.author	Hsu, Chung-Wei	en_US
dc.contributor.author	Hou, Tuo-Hung	en_US
dc.date.accessioned	2017-04-21T06:49:21Z	-
dc.date.available	2017-04-21T06:49:21Z	-
dc.date.issued	2014	en_US
dc.identifier.isbn	978-1-4799-8000-0	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136406	-
dc.description.abstract	A high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM is proposed as an energy- and cost-efficient neuromorphic computation hardware. The device shows excellent analog synaptic features that can be accurately described by the physical and compact models. Ultra-low energy consumption comparable to that of a biological synapse (<10 fJ/spike) has been demonstrated for the first time.	en_US
dc.language.iso	en_US	en_US
dc.title	3D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic Computation	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000370384800165	en_US
dc.citation.woscount	0	en_US
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