完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorWang, H. T.en_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorChang, Wayneen_US
dc.contributor.authorWang, S. D.en_US
dc.contributor.authorChen, C. H.en_US
dc.date.accessioned2017-04-21T06:49:07Z-
dc.date.available2017-04-21T06:49:07Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4673-8258-8en_US
dc.identifier.issn1946-1550en_US
dc.identifier.urihttp://hdl.handle.net/11536/136410-
dc.description.abstractThe endurance and charge loss are the most critical issue in the design of a SONOS memory cell. The origin of the window closure and charge loss was partly caused by the electrons and holes mismatch along the channel lateral direction during the cycling. In this paper, two measurement techniques to observe the mismatch of programmed electrons and erased holes have been developed. It was demonstrated on an MTP (Multi-Time-Programming) SONOS flash memory. By observing the charge distribution, the mismatch which led to window closure and charge loss can be well understood, and better operating schemes can then be developed.en_US
dc.language.isoen_USen_US
dc.subjectSONOS flash memoryen_US
dc.subjectgated-diode measurementen_US
dc.subjectRandom Telegraph Noise (RTN)en_US
dc.subjectenduranceen_US
dc.subjectcharge lossen_US
dc.subjectretentionen_US
dc.titleExperimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile Memoryen_US
dc.typeProceedings Paperen_US
dc.identifier.journalProceedings of the 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)en_US
dc.citation.spage38en_US
dc.citation.epage42en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000389243200009en_US
dc.citation.woscount0en_US
顯示於類別:會議論文