完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, Ming-Hung | en_US |
dc.contributor.author | Lin, Horng-Chih | en_US |
dc.contributor.author | Li, Pei-Wen | en_US |
dc.contributor.author | Huang, Tiao-Yuan | en_US |
dc.date.accessioned | 2017-04-21T06:49:06Z | - |
dc.date.available | 2017-04-21T06:49:06Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-4673-8258-8 | en_US |
dc.identifier.issn | 1946-1550 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136412 | - |
dc.description.abstract | IGZO transistors with various gate/drain-offset lengths (L-GDO) were fabricated with the film-profile-engineering method. Breakdown voltage (V-BD) of the fabricated devices increases while transconductance (gm) decreases with increasing LGDO. In contrast, threshold voltage and subthreshold swing remain relatively unchanged. VBD of similar to 80 V is obtained with LGDO of 0.3 mu m . Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Film-Profile-Engineered IGZO Thin-Film Transistors with Gate/Drain Offset for High Voltage Operation | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | Proceedings of the 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) | en_US |
dc.citation.spage | 272 | en_US |
dc.citation.epage | 275 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000389243200064 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |