Asymmetric Low Temperature Bonding Structure Using Ultra-thin Buffer Layer Technique for 3D Integration

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liang, Hao-Wen	en_US
dc.contributor.author	Yu, Ting-Yang	en_US
dc.contributor.author	Chang, Yao-Jen	en_US
dc.contributor.author	Chen, Kuan-Neng	en_US
dc.date.accessioned	2017-04-21T06:49:06Z	-
dc.date.available	2017-04-21T06:49:06Z	-
dc.date.issued	2016	en_US
dc.identifier.isbn	978-1-4673-8258-8	en_US
dc.identifier.issn	1946-1550	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136413	-
dc.description.abstract	Wafer-level Sn/In-Cu bonding structure with Ni ultra-thin buffer layer is investigated to achieve a reduction in solder thickness, bonding temperature and duration. Furthermore, the asymmetric bonding structure is able to separate the manufacturing process of solder and electrical isolation layer. It is a promising approach for the application on hybrid bonding of three-dimensional integration.	en_US
dc.language.iso	en_US	en_US
dc.title	Asymmetric Low Temperature Bonding Structure Using Ultra-thin Buffer Layer Technique for 3D Integration	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	Proceedings of the 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)	en_US
dc.citation.spage	312	en_US
dc.citation.epage	315	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000389243200073	en_US
dc.citation.woscount	0	en_US
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